The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductor devices and structure.
In the past, the semiconductor industry utilized depletion mode transistors in various configurations and applications. One particular technique utilized two serially connected depletion mode transistors of opposite conductivity types to provide low voltage operation and low leakage current. Such a technique is disclosed in U.S. Pat. No. 6,380,769 issued to Hall et al on Apr. 30, 2002, which is hereby incorporated herein by reference. Forming both N-channel and P-channel depletion mode transistors required extra processing steps to form the N-channel depletion mode transistor and further additional processing steps to form the P-channel depletion mode transistor. Such extra processing steps increased the cost of the semiconductor device using the depletion mode transistors.
Accordingly, it is desirable to have a method of using depletion mode transistors that requires fewer processing operations.
For simplicity and clarity of illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device such as a source or a drain of an MOS transistor or an emitter or a collector of a bipolar transistor, and a control electrode means an element of the device that controls current through the device such as a gate of an MOS transistor or a base of a bipolar transistor.